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80186 Microprocessors: Introduction and Architecture

Hello friends, today we are going to discuss the 80186 microprocessor with integrated peripherals. The Intel 80186 is an improved version of the 8086 microprocessor. 80186 is a 16-bit microprocessor with a 16-bit data bus and a 20-bit address bus. It has a programmable peripheral device integrated into the same package. The instruction set of the 80186 is a superset of the instruction set of the 8086. The term super-set means that all of the 8086 instructions will execute properly on an 80186, but the 80186 has a few additional instructions. The following figure shows the block diagram and pin diagram of 80186. The CPU is divided into seven independent functional parts. 80186 internal block diagram  80186 68-pins pin diagram  Functional parts of 80186 Microprocessor The Bus Interface Unit (BIU) Execution Unit (EU) Clock Generator Programmable interrupt controller Programmable Chip Select Unit (CSU) Programmable DMA Unit Programmable counter/timers The Bus Interface Unit

Bus Structure of Microcomputer

We have already seen the description of what is computer? Today we are going to discuss the detail study of microcomputer buses which communicate with a peripheral devices or a memory location through communication lines called buses.

8085 bus structure
Bus Structure Of Microcomputer

The major parts of microcomputers are central processing unit (CPU), memory, and input and output unit. To connect these parts together through three sets of parallel lines, called buses.  These three buses are  Address bus, data bus, and Control bus.

Address Bus:

The address bus consists of 16, 20, 24, or more parallel signal lines, through which the CPU sends out the address of the memory location. This memory location is used for to written to or read from. The number of memory location is depends on 2 to the power N address lines.  Example, a CPU with 16 address lines can address 216 or 65,536 memory locations. When the CPU reads data from or writes data to a port. The port address is also sent out on the address bus. This is unidirectional. This means that the CPU can send data to a memory location or I/O ports.

Data Bus:

The data bus consists of 8, 16, 32 or more parallel signal lines. The data bus lines are bidirectional. This means that the CPU can read data from memory or from a I/O port as well as send data to a memory location or to a I/O port. In a system, many output devices are connected to the data bus, but only one device at a time will be enabled to the output.

Control Bus:

The control bus consists of 4-10 parallel signal lines. The CPU sends out signals on the control bus to enable the outputs of addressed memory devices or port devices. Typically control bus signals are memory read, memory write, I/O read and I/O write. To read a data from a memory location, the CPU sends out the address of the desired data on the address bus and then sends out a memory read signal on the control bus. The memory read signal enables the addressed memory device to output the data onto the data bus where it is read by the CPU.



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